The invention relates to a a linearity corrected deflection apparatus of a cathode ray tube (CRT).
A horizontal or line deflection circuit produces a horizontal deflection current in a horizontal deflection winding that is mounted on a neck of a CRT. Line deflection circuits are subject to asymmetrical horizontal linearity errors caused by losses in the horizontal deflection winding and the trace switch.
Typically, a CRT having a reduced length or depth is formed with an increased deflection angle. A CRT with a deflection angle greater than 110xc2x0 requires a large amount of inside and outside pincushion distortion correction. A large amount of these distortion corrections require extensive amplitude and frequency modulation of the deflection current at a vertical rate. All these increased modulations of the deflection current increase horizontal linearity distortion.
An active linearity correction circuit is described in U.S. Pat. No. 4,634,938, in the name of Haferl, entitled, Linearity Corrected Deflection Circuit (The Haferl Patent). In the Haferl Patent, the S-shaping or trace capacitor acquires an additional charge during trace to obtain an increased deflection current during the second half of trace. This additional charge is taken out of the trace capacitor during retrace to avoid a DC component in the deflection current. In the Haferl Patent, an inductor is responsive to a deflection retrace pulse voltage for supplying a correction current to the trace capacitor, during the trace interval.
A deflection apparatus with raster distortion correction, embodying an inventive feature, includes a deflection winding. A retrace, first capacitance is coupled to the deflection winding to form a retrace resonant circuit with the deflection winding, during a retrace interval. A trace, second capacitor is coupled to the deflection winding to form a trace resonant circuit with the deflection winding, during a trace interval. A source of a synchronizing signal at a frequency related to a first deflection frequency is provided. A first switching semiconductor is responsive to the synchronizing signal and coupled to the deflection winding and to the retrace first capacitance to generate a first retrace pulse voltage in the retrace, first capacitance, during the retrace interval, and a deflection current in the deflection winding. A charge holding, third capacitance is provided. A sampling switching semiconductor is responsive to the first retrace pulse voltage and coupled to the third capacitance for sampling the first retrace pulse voltage and for developing a sampled voltage from a charge stored in the third capacitance. The sampled voltage is indicative of a magnitude of the first retrace pulse voltage. A first inductance is coupled to the third capacitance for applying the sampled voltage to the first inductance, during the trace interval, to generate a current in the first inductance. The first inductance current is coupled to the trace, second capacitor for varying, in accordance with the first inductance current, a trace voltage in the second capacitor to provide raster distortion correction.
Using the charge holding third capacitor provides design flexibility for obtaining the desirable waveform of the correction current.